1. Field of the Invention
The present invention relates to a timing clock generation circuit installed in a synchronous integrated circuit device, or the like, and which adjusts the phase of the reference clock and generates a prescribed timing clock. Furthermore, the present invention relates to a timing clock generation circuit using a hierarchical DLL which comprises a rough DLL circuit having a rough variable delay circuit controlled in rough delay units and a fine DLL circuit having a fine variable delay circuit controlled in fine delay units. In the case where the phase of the reference clock is temporarily changed by noise or the like, and in the case where the reference clock fluctuates, the timing clock generation circuit relating to the present invention can prevent unnecessary changes to the phase of the timing clock generated.
2. Description of the Related Art
A synchronous integrated circuit device such as synchronous dynamic RAM (SDRAM) synchronizes with a reference clock supplied from outside or operates an internal circuit in a prescribed phase relationship with a reference clock. Such a device therefore includes a timing clock generation circuit for internally regulating the phase of the reference clock and generating a timing clock.
Such a timing clock generation circuit uses a DLL circuit to eliminate the effects of the propagation delay of the reference clock within the integrated circuit device. Specifically, the DLL circuit comprises a variable delay circuit that delays the reference clock and outputs a timing clock, and a phase comparing/delay controlling circuit that compares the phase of the reference clock with the variable clock delayed thereby and adjusts the delay of the variable delay circuit so that those phases match. The basic constitution of such a DLL circuit is disclosed in Japanese Patent Laid-open No. 10-112182 (published Apr. 28, 1998).
The variable delay circuit within the abovementioned DLL circuit comprises multiple connected delay unit circuits having prescribed delay units. Consequently, when the number of the delay unit is changed, the phase of the timing clock generated by the variable delay circuit is changed by an amount equal to one delay unit. Such a change by one delay unit is called a quantization error; according to such an error, the timing clock has jitter (fluctuates) corresponding to the quantization error. It therefore becomes difficult to correctly match the phase of the timing clock with the reference clock.
In Japanese Patent Application No.09-203315 (application date: Jul. 29, 1997) and U.S. patent application Ser. No. 09/089,397 (application date: Jun. 3, 1998), for example, the applicant has proposed a hierarchical DLL circuit using a rough DLL circuit and fine DLL circuit, in order to minimize this jitter and to precisely match the phase of the timing clock with the reference clock.
Such a hierarchical DLL circuit can match the phase of the timing clock with the reference clock with good precision by regulating the phase of the timing clock in rough delay units with the rough DLL circuit, while regulating the phase of the timing clock in smaller delay units with the fine DLL circuit.
Even when such a hierarchical DLL circuit is used, however, the delay of the variable delay circuit is adjusted in rough delay units when the phase of the externally supplied reference clock undergoes a large, temporary shift due to a cause such as power source noise or the like. As a result, jitter from the large rough delay units is generated in the timing clock during the interval until the next phase comparison. When such major jitter is generated, normal control of the internal circuit according to the timing clock cannot be carried out.
Furthermore, when the reference clock supplied from outside has uniform jitter (fluctuation), phase adjustment in fine delay units repeated for ever; sometimes the fine DLL circuit does not lock on. In that case, the timing clock also continues to have unlimited jitter and normal control of the internal circuit according to the timing clock cannot be carried out.
It is an object of the present invention to provide a timing clock generation circuit using a hierarchical DLL circuit that can minimize jitter of the timing clock, even when the phase of the reference clock is temporarily shifted because of noise or the like.
Furthermore, it is another object of the present invention to provide a timing clock generation circuit using a hierarchical DLL circuit that can fix the phase of the timing clock generated even when the reference clock includes uniform jitter.
Furthermore, it is another object of the present invention to provide a timing clock generation circuit using a hierarchical DLL circuit that can minimize jitter of the timing clock even when the phase of the reference clock is shifted temporarily due to noise or the like, and furthermore, can match the phase of the timing clock, beyond the delay control range of the fine variable delay circuit, even when the phase of the reference clock varies.